Special Sessions
The ISVLSI 2025 is inviting proposals for special sessions that explore emerging trends and concepts covering a broad range of topics in the area of VLSI. In particular, special sessions (academic and industrial) concerning hot topics in VLSI, including those dealing with the introduction and discussion of emerging problems, or addressing recent technical trends in computer architecture, IoT systems, security, artificial intelligence and machine learning, edge intelligence, data analytics, autonomous systems, and other that are of interest to ISVLSI participant, are encouraged to apply.
- Special sessions typically run for 1.5 – 2 hours and will consist of minimum 4 papers per session.
- Each speaker at a special session has to submit a 1-page extended abstract for inclusion in the conference proceedings.
- In addition to the extended abstract, each speaker may submit a full paper (up to maximum 6 pages) for inclusion in conference proceedings. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements.
- All papers/extended abstract will be reviewed before being published in the official proceedings of the conference in a separate track.
- Special session organizers are welcome to present their own research in their organized sessions.
- The online submission system (Paper Submission Page) will be used for review of the proposals as well as individual papers.
- Detailed submission instructions will be provided upon acceptance of the proposal.
Submission Guidelines:
Prepare a single PDF file (not exceeding 3 pages), using the template, for the proposal where you:
- describe the session topic, the format, and intended audience, and
- include a list of speakers, their biographical sketch, presentation titles and short abstract.
Submit your special session proposal in EasyChair. (See Paper Submission Page for more details).
For questions regarding the special sessions please contact:
Paper submission guidelines for Special Sessions
Prepare a single PDF following the conferences author guidelines.
Authors can submit their papers for the special sessions of IEEE ISVLSI 2025 via EasyChair, targeting one of the special sessions listed in the sequel.
List of Special Sessions
SS #01: Emerging System Design Topics in New Generation Wireless Communication Technologies (NewGenWT)
SS #02: Advanced Electronics for Smart Agriculture (AESA)
SS #03: Memory Built-In Self-Test : Advanced Techniques for SoC Design and Verification (MBIST)
SS #04: Security By Design (SbD)
SS #05: Secure and Sustainable AI for Cloud to Thing Continuum (SSAI-CTC)
SS #06: Repurposing EDA for Unlocking Emerging Technologies (EDA-UET)
SS #07: Efficient AI algorithms and their hardware implementation (AI-HW)
SS #08: Atom to Zillion: How to Do Computing? (A2Z)
SS #09: Designing Robust, Resource-Constrained Dynamic Deep Neural Networks for Edge AI (RRAI)
SS #10: Smart Healthcare Technologies (SHT)
SS #11: Revolutionizing In-Memory and In-Sensor Computing Architectures (MInSenseCA)
SS #12: Physical Unclonable Functions for Trusted Electronics (PUFTE)
SS #01: Emerging System Design Topics in New Generation Wireless Communication Technologies (NewGenWT)
With the advent of New Generation Wireless Communication technologies like 5G/6G and widespread of IoT networks, challenging KPIs are put forward in terms of bandwidth requirements, delay minimization, massive connectivity capabilities, integrated sensing and communication capabilities, power consumption minimization etc. which are critical in order to deliver novel services in verticals like smart cities, automated driving, security, healthcare, localization and many more. For such capabilities to be delivered, significant advancements are proposed concerning the wireless communication interfaces at either system design level, hardware level as well as signal processing accelerators. In this context, this special session will focus on promoting and presenting high quality research efforts in areas like (but not limited to) smart MIMO system design, reconfigurable intelligent surfaces, fluid antennas and smart signal processing approaches at embedded system or hardware level. We believe that such sessions will significantly expand the scope of ISVLSI communication and allow to form collaborations of high added value and impact.
For questions regarding the specific special session please contact:
SS #02: Advanced Electronics for Smart Agriculture (AESA)
This session explores cutting-edge advancements in IoT, AI, and VLSI tailored to smart agriculture. It focuses on precision farming, resource management, and autonomous systems for sustainable farming practices. The session aims to bridge the gap between academia, industry, and farming communities by presenting practical, impactful solutions.
For questions regarding the specific special session please contact:
SS #03: Memory Built-In Self-Test: Advanced Techniques for SoC Design and Verification (MBIST)
As System-on-Chip (SoC) designs continue to grow in complexity and memory density, ensuring the reliability and testability of embedded memories becomes increasingly critical. This special session presents an in-depth exploration of Memory Built-In Self-Test (MBIST), a powerful methodology for testing and diagnosing memory faults in modern SoC designs. We will discuss the fundamentals of MBIST, advanced implementation techniques, and emerging trends in the field. The session will also cover key aspects of MBIST, including architecture, test algorithm selection, integration in the SoC design flow, and strategies for optimizing test coverage andreducing test time. Through theoretical analysis and practical examples, we will demonstrate how MBIST addresses the challenges of testing high-density memories in complex SoCs, balancing test quality, silicon area overhead, and test time to achieve optimal results in real world scenarios. Additionally, we explore the application of MBIST to emerging memory technologies encompassing non-volatile memories and resistive RAMs. Finally, we will discuss future directions in memory testing, including the use of machine learning and artificial intelligence
For questions regarding the specific special session please contact:
SS #04: Security By Design (SbD)
The concept of "Security by Design" (SbD) has emerged as a critical approach to address the evolving threat landscape and frequency of cyber threats currently of Artificial Intelligence (AI). Internet of Things (IoT) ecosystems are highly affected by these cyber threats. SbD plays a crucial role in Hardware Assisted Security (HAS). Security integrated into the design of the hardware modules can significantly help with the robustness ensuring a secure IoT ecosystems. This special session acts as a platform to invite cutting edge research and solutions in the areas of SbD, HAS, AI – Driven HAS, IoT, and Blockchain to address these problems.
For questions regarding the specific special session please contact:
SS #05: Secure and Sustainable AI for Cloud to Thing Continuum (SSAI-CTC)
The rapid adoption of AI-driven solutions across cloud and edge computing has transformed various industries, including digital water management. This special session at IEEE ISVLSI 2025 explores secure and sustainable AI deployment within the Cloud-to-Thing (C2T) continuum, with a particular focus on AI-enabled hardware solutions for water sustainability.
Key topics include:
- AI on Hardware (FPGA & ASICs): Optimizing energy-efficient AI models for IoT, edge, and cloud environments.
- Security for AI Systems: Addressing vulnerabilities such as hardware attacks and adversarial threats.
- Digital Water Management Applications: Leveraging IoT, edge AI, and cloud computing for water distribution, leakage detection, wastewater management, and pollution control.
With increasing concerns over water scarcity, particularly in Europe and South Asia, this session highlights the role of secure AI hardware in ensuring sustainable resource management. It includes invited talks from leading researchers and industry experts, covering secure AI models, federated learning, watermarking techniques for edge AI, and adaptive computing solutions for multi-access edge clusters.
The session will conclude with a panel discussion addressing global strategies for secure and sustainable AI in digital water management, emphasizing policy-making and future research directions.
This session aims to bridge the gap between AI, VLSI design, and environmental sustainability, fostering interdisciplinary collaboration to develop robust, energy-efficient AI solutions for real-world challenges.
For questions regarding the specific special session please contact:
SS #06: Repurposing EDA for Unlocking Emerging Technologies (EDA-UET)
The continuous scaling of horizontal and vertical features in silicon-based CMOS transistors, known as "More Moore," has propelled the semiconductor industry and technological progress across various scientific fields for decades. Electronic Design Automation (EDA) has been instrumental in this evolution, with advancements in EDA enabling the development of complex systems containing billions or even trillions of transistors.
There has been a profound effort to follow Moore’s law, which continues as we enter the beyond 2nm CMOS era. For several years, density increases from one process node to the next have relied not only on feature scaling but also on design-technology co-optimization (DTCO). By integrating process optimization and system performance evaluation early in development, DTCO enables a holistic approach to advanced nodes and emerging materials/devices. Unlike conventional staged optimization, it simultaneously explores materials, device structures, manufacturing, and system design, enhancing performance and reliability. This demands close collaboration among process engineers, TCAD engineers, and circuit designers. As CMOS technology approaches deep sub-2nm nodes, DTCO becomes even more critical.
Inevitably, CMOS is approaching its limits and will eventually be replaced by "Beyond CMOS" technologies as its scaling reaches atomistic and quantum mechanical boundaries. The neverending need for improving the performance power and area (PPA) of integrated circuits has led “Beyond CMOS” to explore other alternative technologies such as superconducting circuits, quantum computing, etc. Superconducting Single Flux Quantum (SFQ) technologies offer the potential for ultra-low-latency computation with energy dissipation in the order of attojoules per gate, making it an ideal technology for the post-Moore era. Superconducting integrated circuits (ICs) have, therefore, the potential to deliver a tenfold performance boost while consuming a fraction of the power of today’s semiconductor IC. Their unique properties make them key candidates for advancing ultra-sensitive sensing technologies and bridging classical and quantum computing. However, widespread adoption remains challenging, with design automation being a critical area that requires further development. Cryogenic CMOS (or Cryo-CMOS) offers higher performance and lower power without requiring new fabrication methods. Growing interest, driven by scaling challenges and cross-domain innovations, is reflected in rising research and funding. Most importantly, Cryo-CMOS is crucial for linking classical and quantum computing, where qubits require ultra-low temperatures to maintain coherence. CMOS circuits enable this interface but face strict power constraints at cryogenic temperatures, as excessive heat can disrupt qubits. Traditional design automation tools do not account for the altered semiconductor properties at such temperatures, leading to inaccurate power and delay estimations, which hinder their effectiveness in quantum applications.
Additionally, other non-PPA objectives fuel “Beyond CMOS” to explore CMOS alternatives that can fulfill emerging application demands such as sustainability but also ultra-low costs, flexibility, stretchability, conformality, compact form factors, and lightweight designs which traditional silicon technology struggles to achieve. For example, printed and flexible electronics exhibit conformal, porous, and stretchable properties while providing a sustainable solution, e.g., FlexICs based on Indium Gallium Zinc Oxide (IGZO) thin-film transistors dramatically reduce environmental impacts—achieving a 100-fold reduction in water and energy use and a 1,000-fold decrease in carbon footprint compared to silicon-based fabs. However, printed and flexible electronics receive limited support from existing design automation approaches as they mandate alternative computing methods to integrate complex circuits within the underlying technological limitations.
For questions regarding the specific special session please contact:
SS #07: Efficient AI algorithms and their hardware implementation (AI-HW)
The special session is intended to provide an insight into the importance of hardware-software co-design in the field of (embedded) AI. Low-power hardware accelerators for various neural networks are presented, which distribute the complexity of the overall system across both software and hardware, enabling fast and efficient AI execution.
Artificial Intelligence (AI) applications are permeating large areas of business, science and society. Enabled by recent advances in algorithms, computer architectures and big data, AI has made significant breakthroughs in a wide range of applications. The trend in many domains is to shift intelligence from the cloud to the edge. However, integrating AI systems at the edge requires the development of powerful solutions under very tight resource constraints. The use of artificial intelligence (AI) on the Internet of Things (IoT) is primarily limited by energy consumption. Optimised hardware architectures are therefore essential to meet the requirements of such applications. Often, solutions exist that deliver very good results in the high-performance domain, but the use of AI approaches in embedded systems is still a major challenge. Although effective hardware-software codesign methods have been studied for decades, they are still not standard in the development of complex embedded systems, including integrated AI systems.
For questions regarding the specific special session please contact:
SS #08: Atom to Zillion: How to Do Computing? (A2Z)
Computing has evolved from early mechanical machines to modern nanoelectronics, enabling everything from fundamental arithmetic to large-scale artificial intelligence. As the demand for faster, more efficient, and sustainable computing grows, researchers and industries are pushing the boundaries of conventional CMOS-based architectures and exploring beyond-CMOS technologies.
This session will take participants on a journey from the atomic scale of computation—where spin of electrons, novel (2D and memristive) materials, devices (such as STT MRAM, Magnetic skyrmion, emerging memory devices), CMOS and beyond-CMOS circuits and systems etc. come into play—to the zillion-scale, where distributed, edge, and neuromorphic computing power intelligent applications.
For questions regarding the specific special session please contact:
- Sonal Shreya (sshreya@ece.au.dk), Aarhus University, Denmark
- Matteo Farronato (matteo.farronato@polimi.it), Politecnico di Milano, Italy
- Erika Covi (e.covi@rug.nl), University of Groningen, Netherlands
- Amirreza Yousefzadeh (a.yousefzadeh@utwente.nl), University of Twente, Netherlands
- Farshad Moradi (moradi@ece.au.dk), Aarhus University, Denmark
SS #09: Designing Robust, Resource-Constrained Dynamic Deep Neural Networks for Edge AI (RRAI)
Dynamic neural networks represent an emerging research focus within deep learning. In contrast to conventional deep learning models with fixed computational graphs and parameters during inference, dynamic networks can adjust their structures and parameters in response to varying inputs, resulting in significant advantages regarding accuracy, computational efficiency, adaptability and more. Consequently, dynamic networks have garnered substantial research attention in recent years within the fields of computer vision, natural language processing and speech recognition, and recently, an appealing and promising paradigm for inference under resource constrained environments such as those in edge devices.
Their ability to dynamically alter computation during the pipeline (i.e. such as when existing in an early stage), results in potential gains in performance, and savings in terms of energy. Their dynamicity and reconfiguration policies rely on the features appearing on each layer. Various dynamic reconfiguration strategies have for example been proposed. The training of the network is executed in a way that allows it to recognize features based on feature maps acquired from the various layers in the computation pipe – and as a result, their dynamic behavior facilitates efficiency in terms of energy consumption, and performance. Typically, there’s a minor loss of accuracy involved, however, there are several ongoing works focusing on different dynamic reconfiguration strategies, or identification of how the computation should take place, and so on. Their savings in terms of energy, computational complexity and their gains in performance, make early exit dynamic neural networks ideal candidates for deployment on edge accelerators, to address the strict constraints in terms of resources and energy capacity.
As a very relevant topic in low-power, resource constrained Edge AI design, the purpose of the special session therefore is to bring together leaders in edge AI, who will discuss and present their latest findings in design methodologies, tools, platforms and accelerators for designing such dynamic DNNs at the edge. The session aims to address issues related to the performance, energy, accuracy and reliability of such platforms.
For questions regarding the specific special session please contact:
SS #10: Smart Healthcare Technologies (SHT)
With advances in integrated wearable sensing, connected components, and artificial intelligence, it is possible to deploy diagnostic models in the real-world setting for smart healthcare monitoring. Recent research landscape highlights the interest among the scientific community to explore novel sensing and learning methods for non-invasive monitoring of health parameters such as stress, blood sugar, blood pressure, and user behavior.
For questions regarding the specific special session please contact:
SS #11: Revolutionizing In-Memory and In-Sensor Computing Architectures (MInSenseCA)
This special session will explore circuit- and architecture-level innovations in in-memory computing (IMC) and in-sensor computing (ISC), with a strong emphasis on silicon-proven and photonic-hardware prototypes. IMC and ISC paradigms aim to overcome von Neumann bottlenecks by performing computation near or within the memory or sensor interface, dramatically improving energy efficiency and latency for edge AI and real-time signal processing. The session aligns with ISVLSI’s core themes of VLSI systems, low-power design, and intelligent hardware. The talks span a wide range of approaches, including analog and digital ISC, photonic in-memory architectures, processing-in-pixel designs, and cross-layer hardware-algorithm co-optimization. By emphasizing practical hardware implementations—especially those addressing energy-constrained and high-bandwidth applications—this session bridges advanced architectural concepts with emerging silicon and photonic platforms.
For questions regarding the specific special session please contact:
SS #12: Physical Unclonable Functions for Trusted Electronics (PUFTE)
Physical Unclonable Functions (PUFs) are critical for ensuring hardware security, providing unique fingerprints to electronic devices, and combating counterfeiting and unauthorized cloning. This special session complements the IEEE ISVLSI 2025 technical program by focusing on novel materials, innovative designs, and application-oriented methodologies for trusted electronics using PUFs. This topic is timely, given the increasing importance of hardware security and supply chain integrity and is expected to significantly impact the ISVLSI community by bringing together experts working at the intersection of materials science, electronic engineering, cybersecurity, and photonics.
For questions regarding the specific special session please contact: