Abstract:

The rapid evolution of computing is ushering in a new era of pervasive intelligence, fueled by ubiquitous AI, the proliferation of silicon, and the rise of software-driven systems. This talk will explore the potential of next generation computing paradigms, including neuromorphic and quantum computing, in redefining system architectures for the future. Additionally, the speaker will highlight Synopsys’ latest innovations—such as advanced multi-die solutions, SLM, and AI-accelerated tools—designed to empower engineers in building intelligent, high-performance systems that drive the next wave of technological breakthroughs.

Abstract:

The design quality of modern chips depends on the quality of the EDA tools used in the design flow. With the evolution of nanotechnologies new EDA tools are needed. Some trends and Challenges on EDA to cope with the evolution of manufacturing processes will be presented. An important set of EDA tools nowadays are the ones to reduce power consumption at all levels of design abstraction. Power Optimization is fundamental in the IoT world. At logic and physical level, it is needed to reduce the transistor count to reduce leakage power. Also, the use of estimation tools dedicated to each design level and visualization tools are more and more important in modern design flows.

Abstract:

RISC-V is an open-source instruction set architecture (ISA) that has gained significant traction due to its flexibility, modularity, and customization options. This tutorial aims to provide a comprehensive overview of the RISC-V ISA, its design methodology, and the design process.

The following key topics will be covered:

• RISC-V ISA Fundamentals: An exploration of the core elements of the RISC-V ISA, including the instruction set, addressing modes, and privilege levels.
• Customizing the RISC-V ISA: Discussion on the methods and motivations for modifying and extending the RISC-V ISA to address specific application needs.
• RISC-V Design Flow: An introduction to the design flow of a RISC-V processor, including microarchitecture design, register-transfer level implementation, verification, and synthesis.
• RISC-V Toolchain and Ecosystem: An overview of available tools within the RISCV environment, including compilers, assemblers, linkers, simulators, and debuggers.
• RISC-V Applications and Use Cases: A review of various applications and use cases for RISC-V, including examples from AI on edge, embedded systems and high-performance computing.

The tutorial will be led by a team of experts deeply engaged in RISC-V research, development, and application, providing participants with valuable insights and practical knowledge. Attendees will leave with a solid understanding of RISC-V architecture, design, and its application potential.

Abstract:

The rapid proliferation of Large Language Models (LLMs), Graph Neural Networks (GNNs), and other data-intensive AI workloads is pushing the boundaries of compute scalability and energy efficiency. Traditional CMOS-based interconnects and accelerators are increasingly
bottlenecked by thermal constraints, data movement energy, and carbon emissions.

This tutorial addresses a critical and emerging direction: the use of Silicon Photonics (SiPh) to
enable next generation exascale systems that are not only performant but also environmentally
sustainable. We aim to bridge the gap between device-level innovations, circuit and system
modeling, and carbon-aware system architecture for VLSI designers and researchers. By bringing together experts in photonic device modeling and exascale system design, this
tutorial will present a holistic and vertically integrated view that spans:

1. Device modeling (new materials, compact models)
2. Circuit-level simulation of photonic networks
3. Architectural modeling for carbon-optimized acceleration

We will conclude with a hands-on session showcasing open-source tools for photonic device
simulation and system-level evaluation.